HDLBits

module top_module (
    input in,
    output out);
    
    assign out = in;

endmodule

HDLBits

module top_module (
    output out);
	assign out = 1'b0;
endmodule

HDLBits

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~(in2 | in1);
endmodule

HDLBits

module top_module (
    input in1,
    input in2,
    output out);
    assign out = (~in2) & in1;
endmodule

HDLBits

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    assign out = (~(in1 ^ in2)) ^ in3;

endmodule

注意，下图是异或门/同或门。

HDLBits

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a & b;
    assign out_or = a | b;
    assign out_xor = a ^ b;
    assign out_nand = ~(a & b);
    assign out_nor = ~(a | b);
    assign out_xnor = ~(a ^ b);
    assign out_anotb = a & (~b);

endmodule

HDLBits

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);

endmodule

HDLBits

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f = (x3 ? 
        (x2 ? 
            (x1 ? 1 : 0) : 
            (x1 ? 1 : 0)) : 
        (x2 ? 
            (x1 ? 1 : 1) : 
            (x1 ? 0 : 0)));

endmodule

HDLBits